This invention relates to semiconductor devices. More particularly, it is concerned with methods of fabricating junction field effect transistors.
One type of junction field effect semiconductor device which is capable of operation at relatively high frequencies and at relatively high power is the static induction transistor. The static induction transistor is characterized by a short, high resistivity semiconductor channel region which may be controllably depleted of carriers. The current-voltage characteristics of the static induction transistor are generally similar to those of vacuum tube triodes. One form of static induction transistor is the surface-gate static induction transistor (SGSIT) which includes a set of elongated gate regions and a set of elongated source regions interdigitated with the gate regions. In the fabrication of these devices the process of localized oxidation of silicon (LOCOS) is employed to produce silicon dioxide which separates the gate regions from the source regions. Not only does the presence of the oxide provide gate-source separation, but it also has a beneficial effect on the electrical characteristics of the device. Since during the process of fabricating the device silicon oxide is produced by controlled local oxidation of exposed silicon of the body, the process is not sensitive to minor misalignment during the source and gate forming steps or in the patterning of the source and gate metallization.
For static induction transistors which are to operate at frequencies above 1 GHz, semiconductor materials other than silicon are required; for example, compound semiconductor materials such as GaAs and InP. The well-established techniques for the fabrication of silicon surface-gate static induction transistors, however, are not directly applicable to the fabrication of devices employing the other semiconductor materials, since stable native oxides cannot be formed from the compound semiconductor materials. In addition, the same metal cannot be used to make ohmic contact to both P-type regions and N-type regions in these materials as is possible with silicon. Two different types of ohmic metallizations must be separately patterned for the source and gate regions increasing the possibilities of catastrophic misalignment. Furthermore, a third metallization must be deposited and patterned to provide an interconnection of all of the gate regions and an interconnection of all of the source regions to respective bonding pads, thus presenting another possibility for misalignment.